Sputtering, alternatively called physical vapor deposition (PVD), is the most prevalent method of depositing layers of metals and related materials in the fabrication of integrated circuits. Although originally sputtering was principally used to deposit substantially planar layers for horizontal interconnects and other electrical structures, more recently various sputtering techniques have been developed to coat thin, substantially conformal metal or metal nitride layers in holes formed in a dielectric layer. Such holes can be very narrow vias penetrating the dielectric layer to provide vertical electrical interconnections between wiring layers or can be relatively narrow trenches formed in the surface of the dielectric layer to provide horizontal electrical interconnections in the upper wiring layer. Narrow trenches can also be formed in silicon to form trench capacitors for which a thin dielectric gap layer and an inner electrode need to be coated into the trench.
Sputtering technology faces increasing challenges as the feature size of advanced integrated circuits continues to decrease. Sputtering is fundamentally a ballistic process ill suited to coat the walls of high aspect-ratio holes. A typical via structure is illustrated in the cross-sectional view of FIG. 1. A lower dielectric layer 10 includes a conductive feature 12 formed in its surface. The dielectric material is typically based on silicon dioxide although doped silica and other types of low-k dielectric materials are being increasingly used. The conductive feature 12 is usually part of a lower wiring layer and is thus most often composed of aluminum or, in more advanced circuits, copper. The lower layer 10 may alternatively be a crystalline silicon substrate, in which case the conductive feature 12 may be a doped contact region or silicided electrode.
An upper dielectric layer 14 is deposited over the lower dielectric layer 10 and its conductive feature 12. A hole 16 is etched through the upper dielectric layer 14 overlying the conductive feature. The thickness of the dielectric layer 14 is generally constrained to be almost 1 μm in order to prevent dielectric breakdown and to reduce cross talk. However, the width of the via hole 16 in current advanced circuits is about 0.13 μm and technology is being developed for further reductions to 65 nm and below. As a result, the via holes 16 have increasing aspect ratios. Other types of holes 16 are included within the invention, but via holes present some of the greatest challenges.
A barrier layer 18 is deposited onto the sidewalls of the hole 16 and on the planar field region on the top of the dielectric layer 14. In the case of copper metallization, the barrier layer 18 is typically composed of the refractory metal tantalum, or tantalum nitride, or a bi-layer of the two. In the case of aluminum metallization, the barrier layer 18 is typically composed of the refractory metal titanium, titanium nitride, or a bi-layer of the two. The barrier layer 18 prevents diffusion between the dielectric and the metal filled into the hole. Metal diffusing into the dielectric may create a short. Oxygen diffusing into the metallization degrades the metallic conductivity. The barrier layer 18 also acts as an adhesion layer to the dielectric, particularly for copper which does not wet well onto silica. Sputtering techniques, sometimes in combination with chemical vapor deposition (CVD) are available to achieve the barrier structure somewhat idealized in FIG. 1.
A metal seed layer 20 is then deposited in a substantially conformal process. The seed layer 20 is typically composed of the same metal used for the metallization fill, that is, a copper seed layer for copper metallization and an aluminum seed layer for aluminum metallization. It is understood that copper or aluminum may be composed of alloys containing up to 10 wt % of one or more alloying elements as well as the principal copper or aluminum. A field seed region 22 of the seed layer 20 is often relatively thick because of the generally isotropic flux distribution of neutral sputtered atoms. A sidewall seed region 24 presents a challenge in high aspect-ratio holes so that its thickness is small but needs to be continuous. A bottom seed region 26 is advantageously formed to a somewhat greater thickness. After the seed layer 20 has been deposited, the metallization metal is filled into the hole 16 to complete the metallization. For copper metallization, electrochemical plating (ECP) is typically used to fill the hole 16. The copper seed layer 20 both nucleates the ECP copper and serves as the plating electrode. Aluminum fill is most often performed by sputtering so a distinctly different aluminum seed layer is not required. However, the initial stages of aluminum sputtering present some of the same problems to be described for a copper seed layer. For these and other reasons, in very narrow holes, an initial aluminum layer may be sputtered under significantly different conditions such as lower temperature than for the sputter fill aluminum in order to deposit a thin, uniform layer well adhered to the barrier while the higher-temperature fill sputter promotes reflow into the hole so as to avoid any voids.
Sputtering of aluminum or copper targets respectively can be used to deposit either aluminum or copper in a thin nearly conformal layer required for the seed layer 20. Bottom and sidewall coverage can be increased by causing a substantial fraction of the sputtered atoms to be ionized and biasing the wafer to attract the metal ions deep into the hole 16. However, sputtering tends to create overhangs 28 in the seed layer 20 on the upper corner of the hole 16. The overhangs 28 are believed to arise principally from the neutral component of the sputter flux which is somewhat isotropic with approximately a cosine distribution about the vertical axis. Such overhangs 28 may introduce serious problems. The overhangs 28 progressively grow and narrow the throat of the hole 16 during the sputter deposition, thus effectively increasing the aspect ratio and thus further decreasing the sputter flux into the hole 16. Even for an ECP fill, the overhangs 28 present an impediment to the flow of fresh electrolyte. In a worst case, the overhangs 28 can bridge the hole 16 and prevent any further deposition into the hole 16.
Sputter overhangs can be reduced in a number of ways. If the sputter flux is highly ionized, biasing converts the flux distribution to be heavily forward directed and not favoring deposition on the exposed overhang corner and the energetic sputter ions also tend to etch the overhangs. This approach has its own disadvantages. Very high ionization fractions are achieved in reactors including complexly shaped sputtering targets, for example, the single right cylindrical vault of a hollow cathode magnetron (HCM) reactor or the annular vault of an SIP+ reactor, both requiring strong complex magnetrons to increase the plasma density and to direct the flow of sputter ions. Such complexly shaped targets are expensive, a drawback for commercial production. Also, a high bias in the presence of a high ionization fraction may produce a net etching effect in the field region. Not only is no metal deposited there, but the field barrier may be removed.
These techniques, however, become increasingly difficult with narrowing holes. The thicknesses of the barrier and seed layers must be decreased to not unduly reduce the effective width of the already narrow holes. Argon or copper sputtering etching is relatively unselective between the copper and the underlying tantalum. If the barrier layer is exposed either at the hole corner or in the field region, excessive sputter etching is likely to etch through the barrier layer and thus severely affect reliability of the manufactured device. A similar lack of etching selectivity occurs with aluminum and its titanium barrier.
For commercial manufacture, in which yield is a critical economic driver, any advanced process must provide uniform results over the wafer. Otherwise, some of the chips will fall outside the narrow design rules and suffer problems with reliability.
The invention yet further includes flowing argon into a plasma reactor and exciting it into a plasma and then at least partially substituting helium for argon while maintaining the plasma to obtain a helium plasma.